Frame buffer clearing is a frequently used and memory intensive operation in 3D graphics (3DG) applications. As the system on chip (SoC) technology and silicon process advance, 3DG related applications such as games, car navigation, user interface browsing, etc., are becoming popular on portable consumer electronics devices. FIG. 1 shows a typical 3DG SoC, which may include a central processing unit (CPU) 102, a 3DG accelerator 104 or a graphics processing unit (GPU) (not shown), a memory controller 106, an external memory 108 such as static random access memory (SRAM) or dynamic random access memory (DRAM), and a display unit 110. A 3DG application running on the CPU 102 controls the 3DG accelerator 104 to perform such as geometry transformation, lighting operations, texturing and primitive rendering. The rendered result is stored in a frame buffer (FB) 112 resided in the external memory 108, and is passed to the display unit 110. To produce a 3DG scene, a typical 3DG application may go through steps illustrated as follows. The CPU 102 puts 3D object data to the external memory 108. The 3DG accelerator 104 reads object data and processes 3D computations. The 3DG accelerator 104 draws the 3D scene to the frame buffer 112. The display unit 110 reads frame buffer 112 and displays to such as a monitor 114.
FIG. 2 shows a typical OpenGL ES, a popular 3DG application library for embedded systems, commands sequence for 3DG animation. A frame buffer (FB) may consist of a color buffer and a depth (Z) buffer. The rendering of a new frame starts with a buffer clearing operation to reset the storage cells of the color buffer to a background color and the storage cells of the depth buffer to an initial value, as indicated by a glClear command in FIG. 2. The 3D elements are then transformed and drawn on the buffers iteratively, as shown by the inner loop in FIG. 2. After all 3D elements of the current frame have been processed, the frame pointer is mapped to an alternative frame location to start the rendering of the next frame as shown by a glSwapbuffers command and the outer loop in FIG. 2, and a display unit 210 begins to fetch the frame data from the current frame buffer while the next frame is being rendered.
References such as patent documents or literatures disclose technologies for implementations of buffer clearing in such as 3DG applications. For example, an exemplary technology for clearing depth (Z) and color buffers in a real-time graphics rendering system may assign frame flags to pixels, and determine a Z value is valid or not. Instead of filling entire depth and color buffers, the technology only fills the hoes that were not drawn in the previous frame. Another exemplary technology for buffer clearing in 3DG applications may use coordinate values to obtain index values, and gets the content values of corresponding buffer blocks.
Yet another exemplary technology may use mechanisms such as Z compression, fast Z clearing, and hierarchical Z-buffer, for buffer clearing in 3DG applications. For the Z compression mechanism, the Z-buffer is stored in a lossless compressed format to minimize the Z-buffer bandwidth as Z read or write are taking place. For the fast Z clearing mechanism, the bandwidth of another Z-buffer write is used, instead of writing zeros throughout the entire Z-buffer. A fast Z clearing technique is used that may tag entire blocks of the Z-buffer as cleared, such that only each of those blocks need be tagged as cleared. For the hierarchical Z-buffer mechanism, it allows for the pixels being rendered to be checked against the Z-buffer before the pixel actually arrives in the rendering pipelines.
FIG. 3 shows an exemplary method of frame buffer clearing for a graphic rendering system. The method performs a frame dividing step to divide a frame into blocks with each block corresponding to an address of a system memory, and a flag bit (X, Y) is used to record a processing status of each block, as shown in step 310. According to a system reset command, the method changes each flag bit of each block as (X1, Y1) that indicates the block to be changed without performing a clear action, as shown in step 320. According to a system clear command, the method changes each flag bit (X1, Y1) into (X2, Y2) that indicates a clear action must be performed for the blocks, as shown in step 330. The method performs drawing (step 340) after the step 330. Before showing the output after finishing the drawing, the method clears the system memory, which includes performing a clear action for the system memory's addresses corresponding to the blocks with flag bit (X2,Y2), and changing the flag bit (X2,Y2) into (X3, Y3) for the blocks to indicate the blocks have been cleared, as shown in step 350.
Many solutions for buffer clearing in 3DG applications have been suggested. In general, the architectural mechanisms for the solutions may use such as counters, flags, cache, delay and distribution, and so on. Some special memories such as synchronous graphics random access memory (SGRAM), video RAM, etc., are designed for the solutions. These existing techniques still remain issues such as SoC retarget ability because most techniques are dedicated to few or only one device or SoC system. In addition, the issue for performance and power consumption of buffer clearing operations still exist in computer graphic systems.